Timing & Power Analysis CAD Engineer

About Marvell Marvell’s semiconductor solutions are the essential building blocks of the data infrastructure that connects our world. Across enterprise, cloud and AI, and carrier architectures, our innovative technology is enabling new possibilities.  At Marvell, you can affect the arc of individual lives, lift the trajectory of entire industries, and fuel the transformative potential of tomorrow. For those looking to make their mark on purposeful and enduring innovation, above and beyond fleeting trends, Marvell is a place to thrive, learn, and lead.  Your Team, Your Impact As a key CAD member of Marvell Central Engineering, you will play a leading role on developing next-generation automated design flow and its add-on tools. You will have the opportunity to use your extensive design and CAD knowledge to participate in defining the whole organization's design infrastructure, methodology and workflows. What You Can Expect Develop, maintain, and enhance PrimeTime-STA & PrimePower-based power signoff flows within Marvell's M1DP CAD platform. Solid understanding of STA flows including dealing with hierarchical designs Understanding of using Hyperscale & Context models for Hierarchical STA analysis Solid understanding of power estimation flows (average and time-based) Enable and support In-Design Timing & Power flows for timing/power-aware optimization during physical implementation. Collaborate with Physical Design and Front-End teams to set up FSDB/activity files, UPF/CLP power intent, and SAIF/vector annotation for accurate power computation. Develop and maintain glitch analysis and optimization flows, including configuration of glitch-aware datapath optimization settings is a plus Generate, validate, and deliver power analysis reports (dynamic, leakage, glitch) to design teams across multiple ASIC projects by building power dashboard Experience with PrimePower RTL 2.0 adoption for early-stage power estimation, enabling designers to identify and resolve power issues before gate-level analysis is plus Interface with EDA vendors to evaluate new tool features, report bugs, and drive tool improvements. Develop automation scripts (Tcl, Python) to streamline timing & power flow execution, debug, and reporting. Support tapeout activities by ensuring power & timing signoff closure across blocks and full-chip designs. Contribute to knowledge sharing, documentation, and training for timing & power CAD flows across global teams. What We're Looking For B.E./B.Tech or M.E./M.Tech in Electrical Engineering, Electronics Engineering, Computer Science, or a related field. 6 to 10 years of hands-on experience in CAD flow development or power analysis in the semiconductor industry (level-dependent). Proven experience with Synopsys PrimeTime & PrimePower (gate-level and/or RTL-level power analysis). Solid understanding of timing concepts Understanding of advanced node timing effects and variation formats (LVF, POCV & AOCV etc)