Senior/Staff Engineer- ESD Design

About Marvell Marvell’s semiconductor solutions are the essential building blocks of the data infrastructure that connects our world. Across enterprise, cloud and AI, and carrier architectures, our innovative technology is enabling new possibilities.  At Marvell, you can affect the arc of individual lives, lift the trajectory of entire industries, and fuel the transformative potential of tomorrow. For those looking to make their mark on purposeful and enduring innovation, above and beyond fleeting trends, Marvell is a place to thrive, learn, and lead.  Your Team, Your Impact In this position, you will join the Central Engineering team, where you will play a crucial role in establishing ESD requirements and validating ESD solutions for Foundational IP, SerDes IP, and SOCs during the ESD qualification process. You will work closely with the Physical Design, Electrical Engineering, and SOC (System on Chip) teams to provide support from the initial design phase through failure analysis, issue root cause determination, and the development of corrective actions.You will have opportunities for the development of IO circuit to customer specifications including the generation and delivery of final EDA views for the IP. Typical circuits to be developed include biasing blocks, over-voltage/over-current protection circuits, regulators, amplifiers, switches, and a range of closed loop feedback circuits. What You Can Expect Provide co-design support with both ESD simulations of circuits to maximize both performance and ESD protection robustness. Perform ESD design reviews and provide the required technical guidance for analog, foundational IP, SOCs, and qualification test chips for multiple technology nodes ranging from 45nm to A14 across major foundry platforms. Validate and characterize ESD circuits using ICV PERC, Calibre PERC, TLP-based SPICE simulation and any other industry methods and tools. Design enablement of ESD protection schemes for analog design like SerDes. This will include understanding ESD protection design, latch-up, transient latch-up as well as ESD design verification and EDA tools. Continue the development of “best practices” for ESD in the technologies being supported. Development and support of EDA tools for ESD design checking. Development of circuits like Driver, Receiver, Overvoltage protection circuits, Fail safe I/O,Bandgap and Voltage Regulators. What We're Looking For Bachelor’s or master’s degree and/or PhD in Electrical/Electronic Engineering, Microelectronics or related fields and 3-7 years of related professional experience. Expertise in custom circuit design, handling layout effect in advanced FinFET process design rules, process variability and circuit reliability issues that affect power, speed, area, and yield. Advanced knowledge of on-chip ESD protection circuit design Advanced knowledge of CAD design tools such as Cadence and SPICE