Staff/Senior Staff Physical Verification CAD engineer

About Marvell Marvell’s semiconductor solutions are the essential building blocks of the data infrastructure that connects our world. Across enterprise, cloud and AI, and carrier architectures, our innovative technology is enabling new possibilities.  At Marvell, you can affect the arc of individual lives, lift the trajectory of entire industries, and fuel the transformative potential of tomorrow. For those looking to make their mark on purposeful and enduring innovation, above and beyond fleeting trends, Marvell is a place to thrive, learn, and lead.  Your Team, Your Impact We are seeking a highly skilled and experienced Senior Staff Level Physical Verification CAD Engineer to join our dynamic team in Bangalore, India. The ideal candidate will have a deep understanding of the physical verification process in the context of semiconductor design and manufacturing. This role involves working closely with design and layout teams to ensure the integrity and performance of Marvell's advanced semiconductor products. What You Can Expect ​Develop run sets for nanotechnology and support Calibre, ICV and provide user support for DRC and LVS debugging to streamline physical verification flow. Automate and support physical verification flow for internal design tools group. Support tape-out and design-related foundry interface activities, physical verification CAD flow, and CAD flows for SOC integration. Develop and maintain validation procedures for physical verification flow and prepare user guides and documents. Job duties include some usage of full custom layout tools to review results and create validation test cases. CAD and EDA Tool Development: Develop and maintain advanced CAD and EDA tools and methodologies for digital and analog IC design, verification, and physical implementation. Tool Integration: Integrate various EDA tools into an efficient and cohesive design flow, ensuring seamless interoperability and maximizing design productivity. Methodology Development: Define and optimize design methodologies, flows, and best practices for efficient and reliable chip design, from  physical verification to SoC tapeout Design Automation: Automate design tasks, including physical verification flow, design rule decks, automate layout migration, to improve design efficiency and reduce time-to-market. Tool Evaluation and Selection: Evaluate and select third-party EDA tools, libraries, and IPs to meet project requirements, considering performance, scalability, and cost-effectiveness. Collaboration and Support: Collaborate with cross-functional teams, including, foundry engineers, design engineers, layout designers, and software developers, to provide technical guidance, support, and training on CAD and EDA tools and methodologies. Tool Performance and Maintenance: Monitor and optimize tool performance, addressing any issues or bottlenecks, and ensuring tool reliability, stability, and usability across design projects.