Sr. Staff Engineer, Physical Design - Caches

About SiFive As the pioneers who introduced RISC-V to the world, SiFive is transforming the future of compute by bringing the limitless potential of RISC-V to the highest performance and most data-intensive applications in the world. SiFive’s unrivaled compute platforms are continuing to enable leading technology companies around the world to innovate, optimize and deliver the most advanced solutions of tomorrow across every market segment of chip design, including artificial intelligence, machine learning, automotive, data center, mobile, and consumer. With SiFive, the future of RISC-V has no limits. At SiFive, we are always excited to connect with talented individuals, who are just as passionate about driving innovation and changing the world as we are.   Our constant innovation and ongoing success is down to our amazing teams of incredibly talented people, who collaborate and support each other to come up with truly groundbreaking ideas and solutions.  Solutions that will have a huge impact on people's lives; making the world a better place, one processor at a time.  Are you ready?   To learn more about SiFive’s phenomenal success and to see why we have won the GSA’s prestigious Most Respected Private Company Award (for the fourth time!), check out our website and Glassdoor pages. Job Description: About the Role --  At SiFive, we’re redefining the compute landscape with our industry-leading RISC-V compute platforms. As a Sr. Staff Physical Design Engineer (Caches/Memory Subsystems), you will own the physical implementation of critical memory cache structures and tightly integrated SRAM subsystems, from RTL to GDSII. You will deliver high-performance, dense, and power-efficient memory designs on advanced and legacy process nodes. While your primary focus will be in physical design, we are looking for engineers capable of operating across design-abstraction layers. Caches are the heart of CPU performance, and you will act as a bridge between the architecture, RTL, and implementation teams. By understanding the underlying design, you will help drive co-design optimizations that directly impact the speed, area, and efficiency of our IP. Responsibilities - What you’ll do Own Cache Implementation: Drive the physical design implementation for high-performance cache blocks and memory sub-systems, managing synthesis, place & route, and signoff. Engage in Cross-Abstraction-Layer Co-Design: Go beyond standard implementation by actively participating in Architecture/RTL/Implementation co-design. Understand the cache micro-architecture to suggest RTL tweaks, pipeline strategies, or custom macro arrangements etc. that resolve physical bottlenecks. Solve Memory-Specific Challenges: Tackle physical bottlenecks unique to cache design, including highly dense SRAM macro placement, complex routing over macros, critical path timing through memory arrays, and strict dynamic/leakage power management.