CPU Design Verification Engineer II

About SiFive As the pioneers who introduced RISC-V to the world, SiFive is transforming the future of compute by bringing the limitless potential of RISC-V to the highest performance and most data-intensive applications in the world. SiFive’s unrivaled compute platforms are continuing to enable leading technology companies around the world to innovate, optimize and deliver the most advanced solutions of tomorrow across every market segment of chip design, including artificial intelligence, machine learning, automotive, data center, mobile, and consumer. With SiFive, the future of RISC-V has no limits. At SiFive, we are always excited to connect with talented individuals, who are just as passionate about driving innovation and changing the world as we are.   Our constant innovation and ongoing success is down to our amazing teams of incredibly talented people, who collaborate and support each other to come up with truly groundbreaking ideas and solutions.  Solutions that will have a huge impact on people's lives; making the world a better place, one processor at a time.  Are you ready?   To learn more about SiFive’s phenomenal success and to see why we have won the GSA’s prestigious Most Respected Private Company Award (for the fourth time!), check out our website and Glassdoor pages. Job Description: Summary As a Staff Hardware Engineer in Design Verification of CPU, you will own verification strategy and execution for complex out‑of‑order (OOO) processor and cache/memory subsystems. You will define methodology, lead testplan creation, and drive verification of speculative execution, memory ordering, and coherence features from architecture through tape‑out. Key Responsibilities Verification Ownership Own verification of OOO core subsystems, e.g.: Front‑end: fetch, branch prediction, instruction decode, rename. Back‑end: scheduler/issue queues, execution units, bypass networks. Retirement & recovery: ROB, commit, exceptions, interrupts, mispredict recovery. Good knowledge on execution pipelines and multiple execution pipeline scenarios. Memory subsystem: LSU, TLBs, MMU, L1/L2 caches, coherence, fences, atomics. Define verification strategy and test plans from ISA + micro‑architecture specs, with emphasis on: Speculative execution, forwarding, hazards, and replay mechanisms. Memory consistency model (e.g. RVWMO, TSO) and ordering rules. Coherence/consistency interactions across multi‑core systems. Drive coverage closure (functional, code, assertion, and scenario coverage) to sign‑off criteria. Testbench Architecture & Implementation Architect constrained‑random, coverage‑driven UVM testbenches for: OOO core pipeline (including scoreboards and scoreboard‑driven checking). Cache/memory hierarchy, TLB/IOMMU, and coherence protocols. Develop reusable verification components: generators for OOO stress (back‑to‑back branches, deep speculation, dependency patterns), monitors, scoreboards, and protocol checkers.