Lead Engineer – IC Verification

Silicon Labs (NASDAQ: SLAB) is the leading innovator in low-power wireless connectivity, building embedded technology that connects devices and improves lives. Merging cutting-edge technology into the world’s most highly integrated SoCs, Silicon Labs provides device makers the solutions, support, and ecosystems needed to create advanced edge connectivity applications. Headquartered in Austin, Texas, Silicon Labs has operations in over 16 countries and is the trusted partner for innovative solutions in the smart home, industrial IoT, and smart cities markets. Learn more at www.silabs.com. The Role In this role, you will work on verifying complex digital RTL blocks within wireless modem baseband and PHY-layer subsystems that power Wi-Fi and low-power IoT devices. You will play a key role in ensuring the functional correctness, performance, and reliability of modem IPs used in Silicon Labs' wireless SoCs. This is a great opportunity for an experienced Design Verification Engineer who enjoys solving complex technical challenges, developing robust verification environments, and working closely with design and systems teams to deliver high-quality wireless solutions. Meet the Team Our Modem team develops digital baseband and PHY-layer IPs that enable wireless connectivity across Wi-Fi and low-power IoT applications. As part of this team, you will collaborate closely with RTL designers, modem system engineers, verification engineers, and SoC teams to verify complex modem IPs and ensure seamless integration into wireless SoCs. Responsibilities As a Lead IC Verification Engineer on the Modem team, you will: Develop and maintain SystemVerilog/UVM-based verification environments for modem digital baseband and PHY-layer IPs. Design and implement module-level and subsystem-level testbenches, including drivers, monitors, agents, scoreboards, and coverage models. Define and execute comprehensive verification plans to ensure functional correctness and design quality. Drive constrained-random verification, functional coverage, and coverage closure. Perform bit-exact verification by integrating C-based algorithmic reference models into verification environments. Verify complex mixed-signal datapath and PHY-layer modules used in wireless communication systems. Debug complex RTL and testbench issues, working closely with design and system engineering teams to identify root causes. Collaborate across functional teams to resolve integration challenges and ensure successful IP verification and delivery. Participate in design reviews, verification planning, and continuous improvement of verification methodologies. Skills You Will Need Bachelor's or Master's degree in Electrical Engineering, Electronics, Communication Engineering, or a related field. 7–15 years of experience in RTL Design Verification, preferably involving mixed-signal datapath, modem baseband, or PHY-layer modules. Strong hands-on expertise in SystemVerilog and UVM verification methodologies.