Senior Engineer – IC Verification

Silicon Labs (NASDAQ: SLAB) is the leading innovator in low-power wireless connectivity, building embedded technology that connects devices and improves lives. Merging cutting-edge technology into the world’s most highly integrated SoCs, Silicon Labs provides device makers the solutions, support, and ecosystems needed to create advanced edge connectivity applications. Headquartered in Austin, Texas, Silicon Labs has operations in over 16 countries and is the trusted partner for innovative solutions in the smart home, industrial IoT, and smart cities markets. Learn more at www.silabs.com. Meet the Team  The IoT Digital team is a state-of-the-art IC design team focused on producing world-class Wireless MCU SoCs. The team is responsible for architecture specification, design, verification, and implementation of these SoCs, which combine an embedded CPU system with analog and digital peripherals, advanced security, state-of-the-art power management, and best-in-class radios for a wide range of wireless IoT applications and standards.  About the Role  As a Design Verification Engineer, you will work closely with IC Design, System, and Architecture teams to develop and execute verification plans for the next generation of IoT chips. You will contribute across block and IP verification, mixed-signal integration, and SoC-level use-case validation. The role is suited to an Engineer or Senior Engineer at IC3; candidates with strong fundamentals will be considered alongside experienced candidates.  You will help ensure that designs meet their specifications through well-planned stimulus, assertions, coverage, and debug. You will also contribute to low-power verification and improve the flows and methodologies used to develop and integrate IP.  This is an opportunity to contribute directly to the quality and delivery of next-generation Wireless MCU SoCs.  Responsibilities  Perform block- and IP-level verification to validate functionality, performance, and compliance with design requirements.  Develop and execute verification plans based on architecture and design specifications, defining appropriate scenarios and closure criteria.  Architect, implement, and maintain testbenches using SystemVerilog and UVM, including constrained-random stimulus, checkers, and assertions.  Define and analyze functional coverage, identify gaps, and drive verification closure through coverage and regression analysis.  Apply formal verification techniques to mixed-signal IP integration, including verification using real-number models (RNM).  Integrate and verify SoC benches; define, test, and debug system use cases in collaboration with IC Design, System, and Architecture teams.  Verify and debug low-power design behavior, including relevant power-management scenarios and interactions.  Investigate failures, perform root-cause analysis, and communicate issues and verification status clearly to cross-functional teams.