Silicon Domain Architect

Job Details: Job Description: About the Role and Team The AI Silicon Architecture and Performance Engineering team is responsible for developing and maintaining performance models that enable architecture exploration, design evaluation, scalability analysis, and performance projection for next-generation AI silicon products. These models are a critical component of the product development process, providing early visibility into architectural tradeoffs, bottlenecks, and optimization opportunities long before silicon availability. We are seeking a highly experienced and motivated engineer to drive AI silicon performance modeling, validation, architectural analysis, and stakeholder engagement activities. The candidate will work closely with architects, performance stimulus generation teams, silicon design teams, and product stakeholders to evaluate and optimize key AI silicon subsystems that determine overall platform scalability and performance. The role focuses on performance modeling and analysis of AI SoC communication fabrics, memory subsystems, scale-up and scale-out interconnects, host-device memory paths, and end-to-end data movement infrastructure. The successful candidate will leverage SystemC/TLM-based modeling methodologies to generate actionable insights that directly influence architecture and product decisions. This position requires a unique combination of software development expertise, architecture understanding, analytical problem solving, and cross-functional technical leadership. The engineer will be expected to independently drive complex technical initiatives while serving as a trusted performance expert across multiple organizations. ________________________________________ Key Responsibilities 1. AI Silicon Performance Model Development • Develop, maintain, and enhance SystemC/TLM-based performance models representing critical AI silicon subsystems. • Drive modeling of key architectural components including: o SoC fabrics and on-chip communication networks o Memory controllers and memory subsystem behavior o Scale-up controllers and fabrics enabling accelerator-to-accelerator communication within a node, tray, or pod o Scale-out controllers and fabrics enabling communication across nodes, racks, and larger AI clusters o Host CPU to accelerator memory paths o Local, host, and remote memory access paths o End-to-end data movement architectures • Implement new architectural features and capabilities based on evolving product requirements. • Improve model fidelity, scalability, maintainability, and simulation performance. • Perform detailed debugging and root-cause analysis of model issues and performance anomalies. • Contribute to the evolution of modeling infrastructure, methodologies, and best practices. ________________________________________ 2. Functional Validation and Model Correlation • Define and execute comprehensive validation strategies to ensure correctness and architectural accuracy of performance models.