Physical Design Technical Leader | ASIC/SoC physical design

Meet the Team Cisco’s Silicon One Optics Group (S1O) designs & delivers the high-speed optical transceivers, and platforms that power Cisco's core data center networking solutions. We specialize in the design and integration of innovative IM/DD optics and silicon photonic platforms that enable customers to deploy industry-leading optical technologies within data center with unprecedented speed, capacity, and reliability. Come join us and take part in shaping S1O’s ground-breaking optical solutions by designing, developing, and testing some of the most advanced pluggable, and Co-packaged Optics (CPO) being developed in the industry. You will work with Cisco's best-in-class Silicon Photonics team. Our team is responsible for driving the development and optimization of optical transceivers & modules (800G,1.6T & beyond) that seamlessly integrate with Cisco's routing, switching, and datacenter platforms, enabling customers to build scalable, high-performance networks that support emerging technologies including AI/ML workloads, and next-generation data center architectures. Your Impact We are seeking an experienced Physical Design Technical Leader to guide our engineering team and drive physical implementation for Cisco's next-generation silicon photonics driver and receiver ICs, powering 100G, 200G, and 400G-per-lambda Co-Packaged Optics (CPO) and optical engine solutions. In this high-impact role, you will lead the physical design strategy and execution for high-performance silicon integrating sophisticated digital control logic, CPU subsystems, high-speed standard interfaces (UCIe), and ultra-fast transmit/receive data-paths in groundbreaking process nodes (TSMC sub-5nm/3nm/2nm). As a Technical Leader, you will own block-level and full-chip physical implementation from synthesis through final tape-out (TO) while advising, mentoring, and scaling a team of physical design engineers. You will establish advanced physical design methodologies, drive floor-planning, place & route, low-skew clock and power distribution, multi-corner timing closure (STA), EM/IR integrity, and DRC/LVS physical verification sign-off. Additionally, you will partner closely with Architecture, Analog Front-End, Layout, and Photonic packaging teams to ensure first-pass silicon success and drive breakthrough execution across the complete product lifecycle from concept to production. Technical & People Leadership: Lead, mentor, and technically steer a team of physical design engineers, driving task allocations, schedule tracking, and design reviews. Full-Flow Ownership: Own full-chip and hierarchical block-level RTL-to-GDSII implementation and sign-off on advanced nodes. Methodology & Flow Innovation: Architect robust, automated backend flows (Innovus / Fusion Compiler, Pegasus / Calibre, Voltus / RedHawk) to boost team productivity and tapeout predictability.