IP Logic Design Engineer

Job Details: Job Description: About the role Altera is looking for a hands-on Senior RTL Design Engineer to lead FPGA design and platform enablement for Altera development kits. This role spans architecture, Verilog/SystemVerilog implementation, Quartus flows and timing closure, board bring-up, interface validation, and system-level debug.  The ideal candidate can move comfortably from a system requirement or board schematic to a robust RTL implementation, then bring the design up on hardware and isolate issues across RTL, board, clocking, reset, memory, transceiver, and software boundaries.  What you will do Define FPGA architecture, microarchitecture, block diagrams, interface behavior, register maps, clocking, reset strategy, and implementation plans for development-kit designs. Design, RTL code, integrate, and maintain reusable synthesizable RTL using Verilog and SystemVerilog. Translate board and system requirements into RTL features, diagnostics, loopback paths, manufacturing-test functions, and example designs. Own the Altera FPGA development flow using Quartus Prime, including project setup, assignments and constraints, synthesis, fitting, static timing analysis, timing closure, configuration, programming, and release readiness. Support board bring-up from first power-on through FPGA configuration, clock and reset validation, memory initialization, interface enablement, and production-readiness testing. Validate interfaces on Altera development kits using internal and external loopback, protocol traffic, stress testing, interoperability testing, and corner-case testing. Work on one or more of the following interface areas: PCIe, Ethernet, DDR/EMIF, high-speed serial transceivers, FMC, QSFP, USB, UART, I2C, SPI, GPIO, and other board peripherals. Create RTL testbenches and simulation environments; use assertions, directed tests, and coverage-oriented techniques to improve design confidence. Lead technical reviews, mentor engineers, communicate risks and status, and provide clear technical direction during cross-functional debug. Collaborate closely with board engineers to review schematics, pin assignments, clock trees, reset and power sequencing, signal-integrity considerations, board revisions, and hardware constraints. Partner with IP, silicon, firmware, board-test, validation, and applications teams to define interfaces, reproduce failures, and drive issues to root cause. Qualifications: Bachelor’s or master’s degree in Electrical Engineering, Electronics Engineering, Computer Engineering, or a related discipline. 10+ years of professional experience in FPGA RTL design, FPGA implementation, board bring-up Strong expertise in Verilog and SystemVerilog for synthesizable RTL design. Proven hands-on experience with the Quartus Prime or equivalent FPGA flow, including synthesis, fitting, timing analysis, timing closure, timing constraints, and hardware/software interaction.