ASIC Engineer – (New Grad) - India Cisco CAG UHR (Evergreen)

The application window is expected to close on: 11/12/2026

Job posting may be removed earlier if the position is filled or if a sufficient number of applications are received.
Meet the Team Come join the Cisco Silicon One team and participate in the design and verification of leading-edge multimillion gate ASICs. Cisco Silicon One is an industry leading Networking Silicon used in all the core Cisco products. These silicon chips are used to build high density, high speed multi-protocol switches and routers for next generation AI networking infra, Datacenters, Campus & Service provider networks. Your Impact Our creative and talented Physical Design team in Bangalore, India. As a member of this team, you will be involved in creating next generation state-of-the-art networking chips in advanced process node. You will drive the backend process through the entire RTL2GDS Implementation flow including hierarchical floor planning, place & route, timing closure, power integrity, static timing verification, physical verification and equivalence checks, with special focus on performance & die size optimization. ASIC Physical Design Engineer Join our physical design team leading-edge multimillion gate ASICs with state-of-the-art sub 5/3/2 nm technologies. If you enjoy solving complex technical challenges and want to build the silicon that powers Cisco's global networking products, this is the right role for you. What You’ll Bring: Eligibility: The requirement is for 2027 graduates only. Project Management: Ability to manage multiple tasks and work toward long-term goals. Engineering Fundamentals: Solid understanding of engineering fundamentals, digital design fundamentals, and technical problem-solving skills. Collaboration: Experience in establishing and sustaining strong relationships with the extended team. Communication: Excellent communication skills (verbal and written). PD Knowledge: As a Physical Design Engineer, you need a strong grasp of digital design, CMOS technology, VLSI principles, timing, and power fundamentals. Comfortable navigating the complete RTL to GDSII flow, spanning logic synthesis and floorplanning through placement, clock tree synthesis, routing, static timing analysis, and physical verification signoff. It is also crucial to understand key metrics like setup and hold timing, clock skew, congestion, IR drop, electromigration, DRC, LVS, PVT corners, and SDC constraints. Finally, having solid scripting skills is essential for automating workflows and streamlining the entire design process. •       Team-player, can-do attitude will work well in a group environment while still being able to contribute on an individual basis and you will find that you'll have lots of fun and thrive in this environment if you enjoy being challenged, learning new ideas, and push yourself to achieve aggressive technology goals. ASIC Design and Verification Engineer Join our team to design and verify leading-edge multimillion gate ASICs.